1. To develop reliable 3D characterisation techniques, protocols and standards to accurately measure (at micron and submicron resolution) dimensional and structural properties of high aspect ratio (HAR>10) TSV interconnects before and after Cu filling: sidewall roughness, via shape, seed- and barrier-layer thickness, sidewall layer conformity, void detection and characterisation, grain size and grain boundary character distribution of the copper grains, crystalline structure, dislocations, stress around the TSV. In addition, for 3D-SICs with high density TSV interconnects, it is important to consider non-destructive wafer measurements as well as statistical data collection to enable the implementation of the measurement techniques in a production environment.
  2. To develop methods to accurately measure the electrical and thermal transport properties of nanostructured copper TSV interconnects in order to establish traceable measurements of electrical conductivity and temperature change in copper as a function of the current density. Modelling of thermal transport in those structures will help to identify the various thermal scattering mechanisms in nanostructured copper grains.
  3. To develop metrology tools, protocols and standards for high lateral and z resolution (sub microns for x-y, nm for z) non-destructive wafer to wafer alignment control before and after bonding as well as the characterisation of the bonding quality of wafers and dies: parameters at die level such as curvature, surface roughness and flatness which might need to be coupled with wafer level information; wafer/die contamination before bonding; wafer/die interface defectivity and adhesion after bonding; local stress and thermal dissipation at the interface of bonding wafers and dies will also be considered.
  4. To provide traceable metrology for thickness uniformity control and for the surface quality of wafers/dies thinning (in the presence of circuits) and measurement techniques related to stress relaxation, crystalline defects and surface contamination.
  5. To engage with the semiconductor industry and others to facilitate the take up of the technology and measurement infrastructure developed by the project, to support the development of new, innovative products utilising 3D-stacked ICs, thereby enhancing the competitiveness of EU industry.
Via depth by WTS sensor

Via depth by WTS sensor (image courtesy of CEA-LETI)