A three year collaborative project between 8 Industries and European National Measurement Institutes; this project will deliver traceable metrological infrastructure required for structural and chemical defects inspection in high aspect ratio through silicon vias (HAR TSV) and wafer/chip bonding and thinning.

In February 2014, the European Electronic Leaders Group, representing the main companies in the sector, identified 3D integration of heterogeneous semiconductor technologies as the key opportunity for growth in Europe [1]. 3D integration technology uses copper Through Silicon Vias (TSV) to electrically connect a stack of chips-bonded semiconductor wafers and dies to produce 3D stacked integrated circuits (3D-SICs) with an optimum combination of cost, functionality, performance and power consumption.

Probing head and scanning table of  the custom-built Near Field Scanning Microwave Microscope

Probing head and scanning table of the custom-built Near Field Scanning Microwave Microscope at METAS (courtesy of METAS)

While this technology is already used in imagers, memories and MEMS, its extension into new areas will require a much larger density of higher aspect-ratio, smaller TSVs. This creates new metrological issues related to the dimensional and electrical characterisation of these TSVs and to the characterisation of heat caused by the higher current density in those structures. Another aspect of this technological vision is that each function of the 3D stack samples (i.e. memory, sensor, biochip) can be manufactured independently at the right node (the node is the number representing the lowest size of the chip features) and in an optimised production line. 3D integration will allow them to be combined into a single compact system, with logic devices, memories, imagers and MEMS structures from different wafers (from various foundries) using different manufacturing processes. However, this introduces new traceability requirements in the metrology (e.g. dimensional measurement) for 3D integration.

This project will establish the measurement infrastructure required by European industries and research laboratories to accelerate the development and adoption of 3D Stacked Integrated Circuits.

[1] A European Industrial Strategic Roadmap for Micro- and Nano-Electronic Components and Systems

Publishable Summary on Euramet site