Impact on relevant standards:
Information on the progress and results of the project will be disseminated to International and European standard bodies and committees in this field and recommendations will be made when appropriate. The consortium already has strong links to advisory and standards committees including: IEC TC47, IEC TC113, ISO TC229 for semiconductors, SEMI for 3D-SIC and ISO TC201 for surface chemical analysis.

Impact on industrial and other user communities:
This project will provide a clear industrial exploitation path towards further functionality for TSV based 3D- SICs devices, while lowering manufacturing costs and time to market. Focusing on industrial needs and having participants who are an integral part of the semiconductor industry value chain (R&D labs, Integrated Device and end-equipment Manufacturers) will ensure an effective transfer of the results of this project into industry, reinforced by work on the standardisation of key technologies, design parameters and processes.

While the technologies provided by this JRP are beneficial for the worldwide adoption of this technology, the European development of the metrology process will allow Europe to play a more important role in the supply chain for future information systems built using highly dense electronics, and will create an enduring competitive advantage for Europe.

The project will also support the Digital Agenda for Europe within the Initiative 2020 Action 129: Pooling of European public and private resources for the micro- and nano-electronics behind a common industrial strategy and the Key Enabling Technologies Initiative (KET) established in 2011. This project will contribute to the European industrial strategy for micro/nano electronics published on 14 February 2014 with the ambitious goal to get around 20 % of semiconductor manufacturing back to Europe by 2020.

Impact on the metrological and scientific communities:
This project will have an immediate impact by providing traceable facilities for the calibration standards and measurements of thermal and electrical material characterisation, defects inspection for high-aspect ratio TSV and wafer/chip bonding and thinning processes to existing European companies through its trade association – European Semiconductor Industry Association (ESIA).